The present invention relates to the field of equalization in high-speed receiving units, particularly to a continuous-time linear equalization. Furthermore, the present invention relates to a continuous-time linear equalizer suitable for the implementation in integrated circuitry, particularly in CMOS technology.
Data transceiving systems for high-speed communication are subject to signal distortion of the transmitted signal. Various measures are applied to reconstruct the transmitted data from the received analog signal. In receiving units, a number of equalizers are commonly provided to compensate for losses and signal distortion substantially caused by propagating the data signal via the transmission channel.
One known measure concerns an equalization of the received analog signal in the continuous time regime, i. e. before sampling and digitization and before the final digital processing of information is performed, by means of a continuous-time linear equalizer. The received analog signal to be processed by the continuous-time linear equalizer corresponds to a continuous voltage or current signal which is transmitted across the physical transmission channel according to a digital modulation format, e. g. to non-return-to-zero binary level signaling or to a pulse amplitude modulation with four signaling levels (PAM-4). It is the general purpose of a continuous-time linear equalization to compensate for the losses of high-frequency components of the transmitted analog signal which are caused by attenuation and dispersion of the signal propagating along the transmission channel.
Continuous time linear equalizers (CTLE) are used in the receiving units in order to equalize the transmission channel attenuation up to a peaking frequency by means of a high-pass transfer function. Generally, CTLE use active peaking transistor arrays followed by integrating summers to achieve an equalization for high-speed data transmission systems. However, for very high-speed transmission systems, the combination of active peaking transistor arrays and integrating summer might not be sufficient in order to reach the required performance, particularly for implementation in a higher integration technology, such as 14 nm CMOS technology.
A challenge for designing continuous time linear equalizers is extending its bandwidth and increasing the peaking available at half-baud frequency. Bandwidth of these continuous time linear equalizers are often extended by inductors. A limitation of the high-frequency bandwidth of conventional approaches can be addressed with passive inductors, as proposed in Bulzacchelli, John F. et al. “A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology”, IEEE, Journal of Solid State Circuits, Vol. 47, No. 12, December 2012. However, passive inductors are usually bulky, i.e. have a high area consumption when integrated in a CMOS technology, have a fixed inductance and provide a substantial temperature dependency.
Document U.S. Pat. No. 8,810,319 B1 discloses a conventional continuous-time linear equalizer design which uses a capacitive-source-degenerated differential wideband amplifier. However, it can only accommodate a limited bandwidth because the bandwidth is heavily dependent on the load capacitance.